" NTSC test signal generator
"
" (C)ChaN, 2004
"
" This will able to be fitted to most CPLD. Following pin numbers are
" for Xilinx XC95108-15PC84 used as U1 in 'NTSC SIGNAL GENERATOR'.

MODULE ntsg


" Inputs
CLK pin 9;                       " Master clock
!RUN, !WE, !FRES, HS pin 36..33; " Operating mode controls
D7..D0 pin 37,39..41,43..46;     " Data gate inputs


" Outputs

Y7..Y0 pin 76..74,72,71..68    istype 'reg'; " Y data gate
U7..U0 pin 67..65,63..61,58,57 istype 'reg'; " U data gate
V7..V0 pin 56..50,48           istype 'reg'; " V data gate

A10..A0  pin 5..1,84..79 istype 'reg_g'; " Line address counter
BY3..BY0 pin 15..12      istype 'reg_g'; " Bank address reg for Y
BC3..BC0 pin 11,10,7,6   istype 'reg_g'; " Bank address reg for U/V

MCLK1 pin 47 istype 'reg';  " MCU clock div (bit1)
!INT pin 32 istype 'com';   " Line start interrupt


" Nodes

Eol, Aen node istype 'com,keep';  " Line timing indicator
Ws1,Ws0      node istype 'reg';   " WR edge detector
MCLK0         node istype 'reg';  " MCU clock div (bit0)


" Symbols/Parameters

D = [D7..D0];
Y = [Y7..Y0];
U = [U7..U0];
V = [V7..V0];

A = [A10..A0];
BY = [BY3..BY0];
BC = [BC3..BC0];

MCLK = [MCLK1,MCLK0];



EQUATIONS

" Line address counter, Bank address register

[Ws1,Ws0,BC,BY,A].clk = CLK;

[Ws1,Ws0] := [Ws0,WE];   " WR edge detector
Aen = RUN # Ws1 & !Ws0;  " Address increment enable. (Running mode or WR rise)
Eol = FRES               " End of line (next returns zero)
    # (A == 1819) & !HS
    # (A == 909) & HS;

A.ce = Aen;              " Next Address when Aen is 1
A := (A + 1) & !Eol;

[BC,BY].ce = Eol & Aen;  " Update banks when line address returns zero
[BC,BY] := D;



" Data transfer gate

[Y,U,V].clk = WE;
[Y,U,V] := [D,D,D];
[Y,U,V].oe = !RUN;



" MCU clock, Line start interrupt

MCLK.clk = CLK;
MCLK := MCLK + 1;
INT = (A < 32);


END