" Universal Counter - Timer/Counter controller
"
" (C)ChaN, 2003, chan@elm-chan.org
" 
" This will able to be fitted to most CPLD. Following pin numbers are
" for Lattice ispLSI2032-80LT44 used as U1 in "Universal Counter".

MODULE uc

" Inputs

CLK,GATE,CLR  pin 9,23,31;
IS0..IS2 pin 36..34;
MS0..MS1 pin 33..32;
FIN0..FIN3 pin 1..4;

" Outputs

CT11 pin 26 istype 'reg';
GEN  pin 25 istype 'com';
EOC  pin 24 istype 'reg_t';
PCLK pin 22 istype 'reg_t';

" Nodes

FMUX,CMUX,GMUX node istype 'com,keep';
CT0            node istype 'reg_t';
CT1..CT10      node istype 'reg';
P1CK,P2CK      node istype 'com,keep';
GTEN           node istype 'reg_t';

" Symbols/Parameters

IS = [IS2..IS0];
MS = [MS1,MS0];
CT = [CT11..CT1];


EQUATIONS

" Multiplexers

FMUX =  (IS == 0) &  FIN0
      # (IS == 1) & !FIN0
      # (IS == 2) &  FIN1
      # (IS == 3) & !FIN1
      # (IS == 4) &  FIN2
      # (IS == 5) & !FIN2
      # (IS == 6) &  FIN3
      # (IS == 7) & !FIN3;

CMUX =  (MS == 0) & FMUX
      # (MS == 1) & GATE
      # (MS == 2) & CLK
      # (MS == 3) & CLK;

GMUX =  (MS == 0) & GATE
      # (MS == 1) & 1
      # (MS == 2) & GEN
      # (MS == 3) & GEN;


" Main counter block

PCLK.clk = CLK;
PCLK.t = 1;

CT0.clk = CMUX;
CT0.t = GMUX;
CT0.ar = CLR;

CT.clk = !CT0;
CT.ar = CLR;
CT := CT + 1;


" Period/Width gating block

P1CK = FMUX $ MS0;
EOC.clk = P1CK;
EOC.t = GEN;
EOC.ar = CLR;

P2CK = P1CK $ MS0;
GTEN.clk = P2CK;
GTEN.t = 1;
GTEN.ar = CLR;

GEN = !EOC & GTEN;


END